This invention relates generally to integrated circuit configurable gate arrays and more particularly to output signal parametric testing circuitry for such gate arrays.
As is known in the art, it is frequently desirable to manufacture an integrated circuit component having a large number of identical logic gates arranged in an array. Once such integrated circuit is manufactured, the gates in the array thereof are selectively coupled in accordance with the requirements of a customer, such interconnection typically being done during the final metallization process. Such an integrated circuit is sometimes referred to as a configurable gate array. In this way, the integrated circuit manufacturer is able to produce a large number of identical integrated circuit gate arrays which are suitable for a wide variety of uses and in response to the particular needs of its customers is able to, in the final metallization process, personalize the integrated circuit to provide the logic functions required by its customer. Typically, the integrated circuit manufacturer's customer provides the integrated circuit manufacturer with a logic or truth table relating the logical combination of input signals to produce the desired output signals. This relationship between logic input signals and logic output signals provides the basic functional requirement of the integrated circuit gate array. Once the final metallization process selectively interconnects the gates to implement the desired functional relationship between input signals and output signals, a function test is performed to ensure that proper "high" or "low" (i.e., logic 1 and logic 0 signals) are produced at each output pin of the integrated circuit gate array in response to logic signals fed to the input pins of such integrated circuit. This test is performed at very high speeds since there are typically many logic inputs. In addition to this functional test, the integrated circuit manufacturer must ensure that the output signals of the gate array are produced with proper voltage and current levels. These output voltage or current levels are tested by a parametric test and the output levels typically measured are:
1. The high-level output voltage (i.e., the voltage at an output terminal for a specified output current I.sub.OH) with input conditions applied that according to the product specification will establish a high level at the output;
2. Low level output voltage (i.e., the voltage at an output terminal for a specified output current I.sub.OL) with input conditions applied that according to the product specification will establish a low level at the output; and
3. Short circuit output current (i.e., the current flowing into an output when that output is short circuited to ground) (or other specified potential) with input conditions applied to establish the output logic level farthest from ground potential (or other specified potential).
To bring each output (one at a time) to the desired low or high state is a very difficult and time consuming task on behalf of test engineer and sometimes requires several weeks of engineering time for a complex Very Large Scale Integration (VLSI) device. One technique used to reduce the test engineer's time is described in co-pending U.S. Pat. application Ser.No. 452,169, filed Dec. 22, 1982, now U.S. Pat. No. 4,527.115, entitled "Configurable Logic Gate Array", inventors Deepak Mehrotra, Rajni Kant and Kishor M. Patel, and assigned to the same assignee as the present invention.
As is also known in the art, when a configured gate array is electrically wired to other electrical components on, for example, a printed circuit board, it is sometimes required to individually test these other electrical components. One way to provide these tests, however, is to un-wire the gate array from the component under test which had been already wired to the component to be tested. After testing the un-wired component, the component, if operative, would have to be re-wired to the other components.